A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT

This paper presents a mixed-decimation multipath delay feedback (M 2 DF) approach for the radix-2 k fast Fourier transform. We employ the principle of folding transformation to derive the proposed architecture, which activates the idle period of arithmetic modules in multipath delay feedback (MDF) architectures by integrating the decimation-in-time operations into the decimation-in-frequency-operated computing units. Furthermore, we compare the proposed design with other efficient schemes, namely, the MDF and the multipath delay com-mutator (MDC) scheme theoretically and experimentally. Relying on the obtained expressions and statistics, it can be concluded that the M 2 DF design serves as an efficient alternative to the MDF scheme, since it achieves improved efficiency in the utilization of arithmetic resources without deteriorating the superiorities of feedback structures. In addition, the recommended design performs better in memory requirement and computing delay compared with the MDC approach. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. Enhancement of the project: Existing System: In the serial-input-serial-output (SISO) scenario, single-path delay commutator (SDC) structure is one of the most classical approaches to perform the pipelined FFT computation. To reduce the memory banks in SDC pipelines, single-path delay feedback (SDF) architecture is proposed, which is characterized by the feedback connections in the circuits. These hardware schemes can be combined with the radix-2, radix-4, and especially radix-2k algorithm to execute the DFT operation. Compared with the radix-4 approach, the radix-2k pipeline is equipped with simpler butterfly units while making a better utilization of complex multipliers than the typical radix-2 The Master of IEEE Projects Copyright © 2016 LeMeniz Infotech. All rights reserved LeMeniz Infotech 36, 100 Feet Road, Natesan Nagar, Near Indira Gandhi Statue, Pondicherry-605 005. Call: 0413-4205444, +91 9566355386, 99625 88976. Web : www.lemenizinfotech.com / www.ieeemaster.com Mail : [email protected] scheme. Thus, radix-2k algorithm acts as an effective alternative to the conventional computation methods from the perspective of hardware design. Admittedly, the extension of communication service has stimulated a dramatic rise of throughput requirements. This advance in real-time business has additionally rendered the hardware schemes designed for SISO applications obsolete to a certain extent. On this occasion, multipath delay commutator (MDC) and multipath delay feedback (MDF), which serve as the upgrade of SDC and SDF, respectively, are proposed to calculate the FFT when several samples of the same sequence are received in parallel. In general, the MDF structure is composed of multiple interconnected SDF paths, and each path is responsible for managing one of the parallel input streams. This design contributes to the inheritance of utilizing registers efficiently at the expense of squandering the arithmetic components, particularly the butterfly units. By contrast, the MDC approach paves the way for boosting the hardware efficiency of arithmetic units (AUs), while additional memories have to be consumed for either reordering the samples or folding the streams, which additionally leads to an increase of computing delay. Disadvantages:  Computing delay is high  Large memory required Proposed System: The top-level design is illustrated in Fig. 1. As shown, the parallel processing includes three phases. 1) Phase 1 (Horizontal DFT Processing): During this phase the operator TS acts on Pparallel data streams x0,..., xP−1 independently to obtain X · TS. The R2kSDF pipelined architecture in series with a bit-reversed reordering unit is a feasible way to implement TS efficiently. 2) Phase 2 (Rotation): The uth (u = 0,..., S − 1) output of Phase 1 in the vth (v = 0,..., P − 1) stream is multiplied by the corresponding twiddle factor e−j2πuv/N to calculate D ʘ X · TS. The Master of IEEE Projects Copyright © 2016 LeMeniz Infotech. All rights reserved LeMeniz Infotech 36, 100 Feet Road, Natesan Nagar, Near Indira Gandhi Statue, Pondicherry-605 005. Call: 0413-4205444, +91 9566355386, 99625 88976. Web : www.lemenizinfotech.com / www.ieeemaster.com Mail : [email protected] 3) Phase 3 (Vertical DFT Processing): P samples within each clock cycle are processed simultaneously through a parallel-input-parallel-output implementation of TP. Parallel output streams y0, y1,..., yP−1 are generated after the execution. Fig. 1. Top-level design of proposed pipelined-parallel hardware structure. DESIGN OF MIXED-DECIMATION MDF ARCHITECTURE Analyzing the SDF Scheme Using Folding Transformation The folding transformation provides a systematic technique for designing control circuits for hardware where several algorithm operations are time multiplexed on a single computing device. Consider an eight-point radix-2k DIF computation, the algorithm can be presented using a data flow graph shown in Fig. 2, where the nodes represent computations and the directed edges represent data paths. The Master of IEEE Projects Copyright © 2016 LeMeniz Infotech. All rights reserved LeMeniz Infotech 36, 100 Feet Road, Natesan Nagar, Near Indira Gandhi Statue, Pondicherry-605 005. Call: 0413-4205444, +91 9566355386, 99625 88976. Web : www.lemenizinfotech.com / www.ieeemaster.com Mail : [email protected] Fig. 2. Data flow graph of an eight-point DIF DFT using a radix-2k algorithm. To boost the hardware efficiency, the implementation scheme can be further optimized by introducing the register minimization technique, which eventually generates the SDF hardware structure presented in Fig. 3. The shift register unit marked nR in the graph indicates that n positions are available in the component to cache the complex inputs. Fig. 3. Optimized hardware scheme to implement the pipelined flow graph. The Master of IEEE Projects Copyright © 2016 LeMeniz Infotech. All rights reserved LeMeniz Infotech 36, 100 Feet Road, Natesan Nagar, Near Indira Gandhi Statue, Pondicherry-605 005. Call: 0413-4205444, +91 9566355386, 99625 88976. Web : www.lemenizinfotech.com / www.ieeemaster.com Mail : [email protected] Design of the M2DF Hardware Structure For the top-level design shown in Fig. 1, the rescheduling strategy proposed in Section III-B is beneficial to optimize the underlying scheme, which results in the proposed M2DF structure. We begin with two-parallel architecture to unfold the kernel. Taking a 32-point DFT computation, for example, the corresponding M2DF design is shown in Fig. 4. Fig. 4. Proposed two-parallel M2DF architectures for the computation of 32-point DFT. (a) Use radix-2 algorithm in the horizontal DFT processing phase. (b) Use radix-22 algorithm in the horizontal DFT processing phase.